The Big Idea
A bus is a set of parallel wires (or traces) that transfers signals between components inside a computer — for example, between the CPU, memory, and I/O devices.
There are three main types of buses:
- Data Bus – carries actual data values.
- Address Bus – carries memory addresses.
- Control Bus – carries control signals.
Each type of bus carries a different kind of information, and therefore their “size” or width is measured in bits, but the meaning of those bits differs.
1. Data Bus
Purpose
Transfers data and instructions between the CPU, memory, and peripherals.
Width
- Typically 8, 16, 32, or 64 bits wide in modern CPUs.
- The width determines how much data can be transferred in one operation.
Example
- A 32-bit data bus can carry 32 bits (4 bytes) per transfer.
- A 64-bit data bus can carry 64 bits (8 bytes) per transfer.
What this means
If the CPU reads a value from memory, the width of the data bus determines how many bits arrive in a single clock cycle.
Example calculation:
64-bit bus → 8 bytes per transfer
CPU frequency: 3 GHz (3×10⁹ cycles/second)
Maximum theoretical throughput = 3×10⁹ × 8 bytes = 24 GB/s (ignoring overhead)
2. Address Bus
Purpose
Carries memory addresses, not data values.
- The CPU uses the address bus to specify which memory location to read or write.
Width
- The width determines how many unique memory locations can be addressed.
- A bus with N lines can address 2ⁿ distinct memory locations.
Examples
| Address Bus Width | Addressable Memory Locations | Addressable Memory Size |
|---|---|---|
| 16 bits | 2¹⁶ = 65,536 | 64 KB |
| 20 bits (8086 CPU) | 2²⁰ = 1,048,576 | 1 MB |
| 32 bits | 2³² = 4,294,967,296 | 4 GB |
| 64 bits | 2⁶⁴ = ~1.84×10¹⁹ | 16 exabytes |
So a 32-bit CPU can access up to 4 GB of unique memory locations directly.
Key point
The address bus doesn’t carry “data,” so we don’t talk about bytes per transfer — it carries addresses, and its width defines the memory range the CPU can reach.
3. Control Bus
Purpose
Carries control and timing signals that coordinate CPU and memory operations.
Each line (or wire) carries one control signal, such as:
- Read/Write (indicates direction of data flow)
- Memory Request / I/O Request
- Clock
- Interrupt Request
- Bus Acknowledge / Ready
Width
- Typically a few to a few dozen lines (e.g., 8–20).
- It’s not about data capacity but about coordination.
Example
A control bus might have:
- 1 line for READ
- 1 line for WRITE
- 1 line for CLOCK
- 1 line for INTERRUPT
- 1 line for RESET
So while the data bus might move 64 bits of data, the control bus might only toggle a few bits per cycle to signal what to do.
Summary Table
| Bus Type | Carries | Width (typical) | Determines | Example Capacity |
|---|---|---|---|---|
| Data Bus | Data & instructions | 8–64 bits | How much data moves at once | 64 bits → 8 bytes per transfer |
| Address Bus | Memory addresses | 16–64 bits | How many memory locations can be accessed | 32 bits → 4 GB |
| Control Bus | Control signals | ~8–20 lines | How CPU and devices coordinate actions | N/A (not measured in bytes) |