The Big Idea
Endianness is the rule a computer system uses to order the bytes of any multi-byte value (such as a 16-, 32-, or 64-bit integer). Because memory is byte-addressable, larger values must be split across consecutive addresses. Endianness specifies which byte is placed at the lowest address and which byte follows.
Please remember in primary memory, the address is not one byte. The data stored at that address is one byte.
- An address is just a number used by the CPU to locate data in memory.
- On a 32-bit system, an address is 32 bits.
- On a 64-bit system, an address is 64 bits.
- The width of the address has nothing to do with how many bytes it stores.
- The memory cell located at each address contains exactly one byte of data.
This is what “byte-addressable memory” means: every unique address identifies one byte of storage.
Example (byte-addressable RAM):
| Address | Data stored at that address |
|---|---|
| 0x1000 | 0x7F |
| 0x1001 | 0x22 |
| 0x1002 | 0x03 |
If you store a 32-bit integer (4 bytes), it must occupy:
| Address | Byte |
|---|---|
| A | b0 |
| A+1 | b1 |
| A+2 | b2 |
| A+3 | b3 |
The addresses are large numeric values, but the contents at each one—what the CPU reads or writes—are always one byte in a byte-addressable architecture.
What Endianness Describes
Every multi-byte value has:
- Most Significant Byte (MSB): the byte containing the highest-magnitude part of the value.
- Least Significant Byte (LSB): the byte containing the lowest-magnitude part.
Example:
For the 32-bit value 0x12345678,
MSB = 0x12, LSB = 0x78.
Endianness determines how these four bytes are arranged in memory addresses A, A+1, A+2, A+3.
How Systems Implement Endianness
CPU Architecture (Primary Mechanism)
Endianness is determined by the processor’s instruction set architecture.
- When the CPU loads or stores a multi-byte word, the hardware automatically applies its native ordering.
- x86/AMD64 use Little-Endian.
- Some architectures (ARM, PowerPC) are bi-endian and can switch modes at boot via control registers.
Operating System (When It Matters)
Although the CPU defines the machine’s native byte order, the OS manages conversions when data crosses system boundaries—primarily in networking.
- Network protocols define Network Byte Order = Big-Endian.
- OS libraries provide byte-swapping functions:
htonl/htons(host → network)ntohl/ntohs(network → host)
Applications rely on these functions so transmitted integers are interpreted correctly on machines with different native endianness.
The Two Formats
1. Big-Endian ("MSB first")
Lowest memory address stores the MSB:
| Address | Byte |
|---|---|
| A | 0x12 |
| A+1 | 0x34 |
| A+2 | 0x56 |
| A+3 | 0x78 |
Used in networking and some older CPU families. Mirrors human numeric notation.
2. Little-Endian ("LSB first")
Lowest memory address stores the LSB:
| Address | Byte |
|---|---|
| A | 0x78 |
| A+1 | 0x56 |
| A+2 | 0x34 |
| A+3 | 0x12 |
Used by nearly all modern desktop/server CPUs. Simplifies arithmetic because the CPU encounters the least significant portion first.
Why Endianness Matters
1. Networking
Systems exchanging binary data must use a common ordering.
If a Little-Endian host sends 0x12345678 as raw bytes to a Big-Endian host, it may be interpreted incorrectly unless conversion to network order occurs.
2. File Formats and Interoperability
Binary file formats, executable formats, and image formats often mandate a fixed endianness. A program reading such files must swap bytes if its host endianness differs.
Examples of cross-endian interactions:
- Little-Endian host → convert to Big-Endian (network order) before sending.
- Big-Endian host → no conversion needed for network order.
- Little-Endian receiver → convert from Big-Endian on arrival.
Summary
Endianness defines how multi-byte values are laid out in memory:
- MSB vs LSB determine significance.
- Big-Endian: MSB at the lowest address (network order).
- Little-Endian: LSB at the lowest address (x86, AMD).
- CPU architecture determines native ordering.
- Operating systems perform byte-swapping for networking and cross-platform data exchange.
Understanding endianness ensures correct interpretation of binary data across different systems and architectures.