The Big Idea

Solid State Drives (SSDs) have revolutionized storage by replacing the mechanical platters and moving heads of traditional Hard Disk Drives (HDDs) with non-volatile flash memory. This results in faster data access, lower latency, better shock resistance, and reduced power consumption. At the core of SSD technology lies NAND flash memory, a type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that allows for persistent data storage without power.

This article provides a detailed examination of how SSDs work, focusing on:

• The structure and behavior of NAND flash cells
• The internal organization of SSDs
• The read/write/erase processes
• Performance considerations
• Wear leveling and reliability strategies

1. NAND Flash Memory Basics

1.1 What Is NAND Flash?

NAND flash is a type of non-volatile memory, meaning it retains data even when power is removed. It is named after the NAND logic gate, which describes the circuit behavior used to control data flow through memory cells.

NAND flash is constructed from floating-gate transistors that trap electrons to represent binary states. Each memory cell can store:

• 1 bit (SLC – Single-Level Cell)
• 2 bits (MLC – Multi-Level Cell)
• 3 bits (TLC – Triple-Level Cell)
• 4 bits (QLC – Quad-Level Cell)

Each additional bit per cell increases storage density but decreases performance and endurance.

2. Flash Cell Operation: Storing and Reading Data

2.1 Memory Cell Structure

Each NAND cell consists of a control gate, an insulating oxide layer, and a floating gate (which stores charge). Logic states are determined by measuring how the stored charge affects the transistor's threshold voltage.

In MLC/TLC/QLC cells, a range of threshold voltages is used to encode multiple bits per cell.

2.2 Reading Data

Reading involves applying a voltage to the control gate and measuring whether the transistor conducts current:

• Conducts: Interpreted as one logical state.
• No conduction: Interpreted as the other logical state.

In multi-bit cells, analog sensing determines which voltage range the cell falls into, mapping it back to a bit pattern.

2.3 Writing Data (Programming)

To write, a process called hot-electron injection is used to trap electrons on the floating gate:

• A high voltage is applied to inject electrons into the floating gate.
• The more electrons, the higher the threshold voltage.

Programming is done at the page level (typically 4–16 KB), but all writes must occur to erased (blank) pages.

2.4 Erasing Data

NAND flash cannot overwrite data in-place. Instead, it uses block-level erasure:

• Entire blocks (usually 128–512 pages) are erased together by applying a high voltage that removes electrons from the floating gate.

This means that modifying a single byte requires copying the entire block, updating the byte, erasing the old block, and writing the new data.

3. Internal Structure of an SSD

Hierarchical Structure:

Die → Plane → Block → Page → Cell

• Page: Smallest unit of read/write (~4–16 KB)
• Block: Smallest unit of erase (~256–512 KB)
• Plane: Contains many blocks
• Die: Contains multiple planes
• Package: Contains one or more dies

Controller:

At the heart of the SSD is the flash controller, which manages:

• Address translation (logical to physical)
• Garbage collection
• Wear leveling
• Error correction
• Encryption (if supported)
• Cache management

DRAM or SLC Cache:

Many SSDs use DRAM for a fast address map (FTL – Flash Translation Layer), and SLC-mode cache to buffer writes for better performance.

4. Core Processes

4.1 Flash Translation Layer (FTL)

Since NAND flash doesn’t allow in-place updates, the SSD uses a mapping layer to translate logical block addresses (LBAs) from the OS to physical NAND locations. This is known as the Flash Translation Layer (FTL).

When data is updated:

• A new page is written elsewhere.
• The old page is marked invalid.
• The FTL updates the mapping.
• Eventually, garbage collection reclaims invalid pages.

4.2 Garbage Collection

Rewrites and deletes produce stale (invalid) pages. To reclaim space:

• Valid data from a block is copied to a new block.
• The old block is erased and returned to the free pool.

This introduces write amplification, where more NAND writes occur than the host requests.

4.3 Wear Leveling

Each NAND cell can endure a limited number of program/erase (P/E) cycles (e.g., ~3,000 for TLC, ~100,000 for SLC). Wear leveling ensures uniform use of all blocks to maximize lifespan:

• Static wear leveling moves infrequently written data to older blocks.
• Dynamic wear leveling distributes writes evenly across free blocks.

4.4 Error Correction

NAND cells degrade over time. SSDs use ECC (Error Correction Code) such as BCH or LDPC to detect and correct bit errors.

5. Performance Considerations

6. Advantages and Trade-Offs

Conclusion

SSDs powered by NAND flash memory offer a sophisticated blend of performance, durability, and efficiency. The internal workings—floating gate transistors, multi-level storage, wear leveling, and flash translation—are hidden behind a controller that provides a simple block interface to the operating system. As SSD technology evolves (with developments like 3D NAND and PCIe Gen5 NVMe), it continues to transform computing, from consumer laptops to data center infrastructures.