A1.1.1 Describe the functions and interactions of the main CPU components.

The Central Processing Unit (CPU) is the "engine" of a computer, diligently executing instructions by processing data, coordinating operations, and managing communication between internal components. It acts as a powerful executor, following instructions provided to it. You will learn more about how instructions are sent to the CPU when you learn about the instruction cycle. If you want to explore this topic in a bit more depth, please take a look at Von Neumann architecture and transitors (but these will not be assessed by the IB).

Detailed Explanation:

1. Main CPU Components: CPU operations involve key components working in close coordination. 

Units:

• Arithmetic Logic Unit (ALU):

  • Function: The ALU performs all the arithmetic operations (e.g., addition, subtraction) and logical operations (e.g., AND, OR, NOT). It's the part that processes numbers and manipulates data according to the instructions it receives.

  • Interaction: The ALU receives the data (operands) it needs for calculations from registers within the CPU. Once the operation is complete, the ALU sends the result back to a register, typically the accumulator (AC), for temporary storage. The Control Unit (CU) dictates precisely which operation the ALU should perform and manages the flow of data to and from it.

• Control Unit (CU):

  • Function: The CU acts as the meticulous director of the CPU's engine. It fetches instructions from primary memory (RAM), decodes them to understand what needs to be done, and then generates precise control signals. These signals orchestrate the activities of all other CPU components, ensuring that each step of an instruction is executed correctly and in the right sequence. The CU itself doesn't execute instructions; it commands the other units to do so.

  • Interaction: The CU is the central coordinator, connecting to and directing all other components within the CPU. It interacts with primary memory to fetch instructions (managing the PC and MAR), receives the instruction via the MDR and IR, instructs the ALU on which operation to perform, and controls the movement of data between all the registers (IR, PC, MAR, MDR, AC) and between the CPU and primary memory via the buses.

Registers:

Registers are small, high-speed storage locations within the CPU, holding instructions and data temporarily for quick access, fueling the engine's immediate needs. A register typically holds one word of data, where the word size depends on the CPU architecture — 8, 16, 32, or 64 bits for general-purpose registers, and up to 512 bits for specialized vector registers.

• Instruction Register (IR):

  • Function: The IR holds the current instruction that the CPU's engine is actively decoding and preparing to execute. It's the blueprint for the immediate action.

  • Interaction: The CU fetches an instruction from primary memory, which is temporarily held in the MDR. The content of the MDR is then copied into the IR. The CU then examines the instruction in the IR to determine the operation and the data (operands) involved, subsequently directing the ALU and other registers accordingly.

• Program Counter (PC):

  • Function: The PC holds the memory address in primary memory of the next instruction that the CPU's engine needs to fetch and execute. It's the pointer that guides the engine to its next task.

  • Interaction: The value in the PC is sent to the MAR, which then places that address on the address bus to fetch the next instruction from primary memory. Once an instruction is fetched, the CU typically increments the PC to point to the subsequent instruction. The CU can also modify the PC's value to implement jumps or loops, altering the flow of execution.

• Memory Address Register (MAR):

  • Function: The MAR holds the specific address in primary memory that the CPU's engine intends to access, either to retrieve instructions or data, or to store data. It's the specific location the engine is currently targeting in the memory store.

  • Interaction: The PC provides the address of the next instruction to the MAR. When data needs to be accessed, the address of that data is also loaded into the MAR by the CU. The MAR then places this address onto the address bus, enabling the memory controller to locate the desired location in primary memory.

• Memory Data Register (MDR):

  • Function: The MDR acts as a temporary buffer, holding the data being transferred between the CPU's engine and the primary memory (RAM). It ensures efficient movement of information into and out of the engine.

  • Interaction: When the CPU reads from primary memory, the data from the location specified by the MAR travels over the data bus and is temporarily stored in the MDR. From the MDR, the CU then moves this data into a register (like the accumulator or a general-purpose register) or the IR (if it's an instruction). When the CPU writes to primary memory, the data to be written is first placed in the MDR by a register, and then the CU initiates its transfer over the data bus to the memory address held in the MAR.

• Accumulator (AC):

  • Function: The accumulator is a register within the CPU's engine that traditionally serves as a primary location for holding one of the operands involved in an ALU operation, as well as storing the immediate result of that operation. While modern CPUs utilize more general-purpose registers, the AC illustrates the direct interaction between the ALU and temporary data storage.

  • Interaction: Before the ALU performs a calculation, one of the values being operated on is often placed in the AC. The other value might come from another register or from primary memory (via the MDR). After the ALU completes the operation, the result is frequently stored back in the AC. The CU then manages the movement of this result to other registers or back to primary memory if needed.

Buses:

These are the communication pathways, the veins and arteries, that allow different parts of the CPU's engine and the system to exchange information. A student asked about how fast a bus is. This is a bit of a tricky questio, but the answer is here. 

• Address Bus:

  • Function: The address bus is a unidirectional pathway that carries memory addresses from the CPU (specifically the MAR) to the memory controller, which then directs the request to the correct location in primary memory. It specifies where the CPU wants to access.

  • Characteristics: Unidirectional (CPU to memory controller).

• Data Bus:

  • Function: The data bus is a bidirectional pathway that transports the actual data between the CPU (specifically the MDR) and the primary memory. This includes both instructions being fetched and data being read or written.

  • Characteristics: Bidirectional (data flows both ways).

• Control Bus:

  • Function: The control bus is a collection of various control signals generated by the CU that coordinate the activities of all components within the system, including primary memory and peripherals. These signals ensure that operations occur in the correct sequence.

  • Characteristics: Bidirectional (CU sends commands; other components can send status signals back).

Processors:

Different designs of the CPU's engine impact its efficiency and capabilities.

• Single Core Processor:

  • Description: An engine with a single processing unit (core) that executes one instruction stream at a time. Multitasking is achieved by rapidly switching between tasks, creating the illusion of simultaneity.

• Multi-core Processor:

  • Description: An engine with multiple independent processing units (cores) integrated onto a single chip. Each core can execute its own instruction stream concurrently, allowing for true parallel processing and significantly enhancing performance for multitasking and multi-threaded applications.

• Co-processors:

  • Description: Specialized auxiliary engines designed to handle specific, computationally intensive tasks, offloading the main CPU. Examples include GPUs (for graphics and parallel computing) and FPUs (for floating-point arithmetic).

Diagrammatic Representation:

Imagine a central Control Unit (CU) with lines of control extending to:

• The Arithmetic Logic Unit (ALU).

• All the Registers (Instruction Register (IR), Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Accumulator (AC)).

• The Memory Address Register (MAR) connected to the unidirectional Address Bus leading to the Memory Controller and then to Primary Memory (RAM).

• The Memory Data Register (MDR) connected to the bidirectional Data Bus leading to the Memory Controller and then to Primary Memory (RAM).

• The Control Bus, also connected to the Memory Controller and Primary Memory (RAM), carrying signals from the CU and potentially status signals back.

The CPU's engine diligently fetches instructions from primary memory, guided by the PC and MAR, decodes them using the CU (stored in the IR), performs calculations in the ALU using data from registers (often involving the AC and MDR), and stores results back in registers or primary memory (via the MDR and MAR), all orchestrated by the CU and facilitated by the address, data, and control buses. The memory controller plays a crucial role in managing the interface between the CPU and primary memory, handling requests for reading and writing data at specific addresses, and is particularly important in advanced memory management techniques like virtual memory.