A1.1.5 Describe the fetch, decode and execute cycle.

📚 You can find additional information in the course companion pages 16 to 21
 

The Big Idea

The fetch–decode–execute cycle describes the ordered sequence of steps that a CPU performs to retrieve an instruction from memory, interpret its meaning, and carry out the corresponding action. Each instruction, stored in binary in main memory, is fetched into the CPU and processed—typically requiring multiple clock cycles for each phase.

Step-by-Step Breakdown

1. Fetch

During the fetch phase, the CPU retrieves the next instruction from main memory (RAM).

Key operations:

1. The Program Counter (PC) holds the address of the next instruction to be executed.
2. This address is copied into the Memory Address Register (MAR).
3. The address is sent to main memory through the address bus.
4. The instruction stored at that memory location is sent back to the CPU over the data bus and temporarily held in the Memory Data Register (MDR).
5. The instruction in the MDR is then transferred to the Current Instruction Register (CIR), where it awaits decoding.
6. Finally, the PC is incremented so it points to the address of the next instruction.

Result:
The CPU now holds the binary instruction in the CIR, ready to be interpreted.

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2. Decode

During the decode phase, the Control Unit (CU) interprets the instruction stored in the CIR. Please click this link to learn about  opcodes and operands. 

Key operations:

• The CU examines the opcode (the part of the instruction that specifies the operation) and determines what the CPU must do.
• If the instruction includes operands (addresses or data values), the CU prepares to retrieve them—possibly using the MAR and MDR again for memory access.
• Internal control signals are generated to direct data movement and select the appropriate ALU operation, register sources, or memory accesses.

Result:
The CPU’s control logic is configured to perform the correct operation in the next phase.

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3. Execute

In the execute phase, the CPU performs the operation specified by the decoded instruction.

Examples of execution:

• Arithmetic or logic operations: Data from registers are processed in the Arithmetic Logic Unit (ALU), with results stored in the Accumulator (AC) or another register.
• Memory operations: The MAR and MDR are used again if data must be read from or written to RAM.
• Control flow operations: The Program Counter (PC) may be updated (for example, in jump or branch instructions).

Result:
The output of the operation is stored in a register, written to memory, or used to modify CPU state (e.g., flags or PC update).

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Interaction with Memory and Registers: The Three Buses

Data and control flow between the CPU and memory are coordinated by three main buses:

Bus	Direction	Purpose	Example during Fetch
Address Bus	Unidirectional	Carries memory addresses from CPU to memory.	PC → MAR → Address Bus → Memory
Data Bus	Bidirectional	Transfers data and instructions between CPU and memory.	Memory → MDR → CIR
Control Bus	Bidirectional	Carries control signals such as read, write, and clock.	CU sends “Read” signal to memory

The MDR acts as the interface between the CPU and the data bus—it temporarily holds data either being read from or written to main memory. The MAR, by contrast, holds the address of the memory location being accessed.

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Visualizing the Cycle (Conceptual Summary)

Fetch:
PC → MAR → Address Bus → Memory → MDR → CIR → Increment PC

Decode:
CIR → Control Unit → Determine Opcode + Operands

Execute:
ALU or Memory Operation → Update Registers/Flags/PC

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Summary

Phase	Description	Key Components Involved
Fetch	Retrieve the next instruction from memory.	PC, MAR, MDR, CIR, Address Bus, Data Bus
Decode	Interpret the binary instruction.	CIR, Control Unit
Execute	Carry out the operation and store the result.	ALU, Registers, Control Bus, MDR (if memory access)

 

In summary, the fetch–decode–execute cycle is the continuous process that underpins all computation in the von Neumann architecture. The MDR and MAR form the essential bridge between CPU and memory, working with the address, data, and control buses to ensure that each instruction moves smoothly from memory to execution.